ON THE VLSI REALIZATION OF COMPLEX INSTRUCTION SETS USING RISC-LIKE COMPONENTS.

Reduced instruction set computers (RISCs) utilize the VLSI chip area more effectively and can outperform complex instruction set computers (CISCs). The authors distribute the processing requirements of a capability-based CISC, oriented toward high-level languages and operating systems, over a number of microprogrammed VLSI coprocessors having RISC-like area-efficient architecture with on-chip cache and address translation hardware. The high-level nature of the coprocessor-executed instructions and data caching on each coprocessor chip overcomes the interprocessor communication overhead, making the overall throughput comparable to that of single-chip RISCs.