Optimal Matrix Multiplication on Faulttolerant VLSI Arrays

The Diogenes methodology, proposed by Rosenberg, for the design of easily testable and configurable faulttolerant VLSI arrays, results in collinear layouts of processors (PE's) that are configured into the desired array structure by appropriate switch settings on buses running parallel to the PE's. While possessing attractive mechanisms for faulttolerant implementations, Diogenes designs of two-dimensional (2-D) arrays require more area than a two-dimensional implementation and result in long wires between logically adjacent PE's. In this paper, we present a collinear VLSI array that retains all the desirable fault-tolerance characteristics of Diogenes designs but avoids the degradation in throughput (caused by a lower system clock rate) that long inter-PE wire lengths would impose. Just as in the systolic model, all signals in our array travel a fixed physical distance in any clock cycle. On this model, we show a lower bound of [formula omitted] on the time complexity required to multiply two n × n matrices by computing the n3 scalar products. Furthermore, we present an optimal [formula omitted] time systolic algorithm using [formula omitted] PE's and requiring O(n2) area. Our algorithm is superior in time performance and/or area requirements to previous matrix multiplication algorithms on this model. The use of retiming enables us to maintain the correctness of our algorithm despite the presence of faulty PE's. Since the clock rate in our design is independent of the number and distribution of faulty PE's, their presence contributes only an additive increase (equal to the number of bypassed faulty PE's) to the time complexity of our algorithm.