TY - GEN
T1 - Optimization of underfill material for better reliability and thermal behavior of 3D packages with TSVs
AU - Kim, Yeonsung
AU - Park, S. B.
PY - 2013
Y1 - 2013
N2 - The demands for a high-density, high-speed, and smaller integrated circuit have resulted in 3D stacked packages with through-silicon via (TSV) technology. Due to their sophisticated structure and complex manufacturing process, however, many issues related to the reliability and thermal management of these 3D packages are still under investigation. Failure at the solder joints between the chip and substrate is inevitable when the 3D package is exposed to thermal loading. The discrepancy in the coefficients of thermal expansion (CTE) between the chip and substrate subjects the solder joints to significant stress and strain. To reduce these thermally induced stresses and strains, an underfill has been used. The optimization of this underfill material is thus one of the most critical issues in improving the reliability and thermal performance of 3D packages. This paper describes a parametric study based on computational fluid dynamics (CFD) analysis to address the junction temperature of the package. The impact on the package temperature of various factors such as the thermal conductivity of underfill, mold compound, substrate, and copper bump ratio was investigated. In addition, the transient heat transfer coefficients from CFD analysis were extracted and used as a thermal boundary condition in thermal and structural finite element analysis (FEA). In thermal and structural simulation, the strain energy at the solder joint was compared by changing the material properties of the underfill. The modulus, CTE, and glass transition temperature (Tg) of the underfill were examined. The most effective material properties were adopted to minimize modeling complexity and reduce computing time. The results of this work should help to design more reliable 3D packages.
AB - The demands for a high-density, high-speed, and smaller integrated circuit have resulted in 3D stacked packages with through-silicon via (TSV) technology. Due to their sophisticated structure and complex manufacturing process, however, many issues related to the reliability and thermal management of these 3D packages are still under investigation. Failure at the solder joints between the chip and substrate is inevitable when the 3D package is exposed to thermal loading. The discrepancy in the coefficients of thermal expansion (CTE) between the chip and substrate subjects the solder joints to significant stress and strain. To reduce these thermally induced stresses and strains, an underfill has been used. The optimization of this underfill material is thus one of the most critical issues in improving the reliability and thermal performance of 3D packages. This paper describes a parametric study based on computational fluid dynamics (CFD) analysis to address the junction temperature of the package. The impact on the package temperature of various factors such as the thermal conductivity of underfill, mold compound, substrate, and copper bump ratio was investigated. In addition, the transient heat transfer coefficients from CFD analysis were extracted and used as a thermal boundary condition in thermal and structural finite element analysis (FEA). In thermal and structural simulation, the strain energy at the solder joint was compared by changing the material properties of the underfill. The modulus, CTE, and glass transition temperature (Tg) of the underfill were examined. The most effective material properties were adopted to minimize modeling complexity and reduce computing time. The results of this work should help to design more reliable 3D packages.
UR - https://www.scopus.com/pages/publications/84883340657
U2 - 10.1109/ECTC.2013.6575906
DO - 10.1109/ECTC.2013.6575906
M3 - Conference contribution
SN - 9781479902330
T3 - Proceedings - Electronic Components and Technology Conference
SP - 2310
EP - 2318
BT - 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
T2 - 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
Y2 - 28 May 2013 through 31 May 2013
ER -