Package reliability: How can we use ideas/methods from semiconductor reliability in package reliability?

Tom Kopley; Scott Pozder; Martin Anselm; Patrick Justison; Matt Ring; Karsten Beckmann; Jeff Siddiqui; Gaddi Haase

doi:10.1109/IIRW.2017.8361249

Package reliability: How can we use ideas/methods from semiconductor reliability in package reliability?

Tom Kopley
, Scott Pozder
, Martin Anselm
, Patrick Justison
, Matt Ring
, Karsten Beckmann
, Jeff Siddiqui
, Gaddi Haase

NY Creates Research Foundation

NY Creates

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Are the fields of fracture mechanics, rheology, etc. good enough to address issues In package reliability? No: JEDEC specs all based on DIP wirebond packages. Are we using results from these fields enough or most effectively? Not addressed. Biggest difference with wafer reliability is stressors on chip are local (E-field, temperature), which stressors in a package are mechanical stress, which is resultant of the entire package materials' CTE.

Original language	English
Title of host publication	2017 IEEE International Integrated Reliability Workshop, IIRW 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-5
Number of pages	5
ISBN (Electronic)	9781538623329
DOIs	https://doi.org/10.1109/IIRW.2017.8361249
State	Published - Jul 2 2017
Event	2017 IEEE International Integrated Reliability Workshop, IIRW 2017 - South Lake Tahoe, United States Duration: Oct 8 2017 → Oct 12 2017

Publication series

Name	IEEE International Integrated Reliability Workshop Final Report
Volume	2017-October

Conference

Conference	2017 IEEE International Integrated Reliability Workshop, IIRW 2017
Country/Territory	United States
City	South Lake Tahoe
Period	10/8/17 → 10/12/17

Access to Document

10.1109/IIRW.2017.8361249

Cite this

Kopley, T., Pozder, S., Anselm, M., Justison, P., Ring, M., Beckmann, K., Siddiqui, J., & Haase, G. (2017). Package reliability: How can we use ideas/methods from semiconductor reliability in package reliability? In 2017 IEEE International Integrated Reliability Workshop, IIRW 2017 (pp. 1-5). (IEEE International Integrated Reliability Workshop Final Report; Vol. 2017-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IIRW.2017.8361249

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title = "Package reliability: How can we use ideas/methods from semiconductor reliability in package reliability?",

abstract = "Are the fields of fracture mechanics, rheology, etc. good enough to address issues In package reliability? No: JEDEC specs all based on DIP wirebond packages. Are we using results from these fields enough or most effectively? Not addressed. Biggest difference with wafer reliability is stressors on chip are local (E-field, temperature), which stressors in a package are mechanical stress, which is resultant of the entire package materials' CTE.",

author = "Tom Kopley and Scott Pozder and Martin Anselm and Patrick Justison and Matt Ring and Karsten Beckmann and Jeff Siddiqui and Gaddi Haase",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE International Integrated Reliability Workshop, IIRW 2017 ; Conference date: 08-10-2017 Through 12-10-2017",

year = "2017",

month = jul,

day = "2",

doi = "10.1109/IIRW.2017.8361249",

language = "English",

series = "IEEE International Integrated Reliability Workshop Final Report",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Kopley, T, Pozder, S, Anselm, M, Justison, P, Ring, M, Beckmann, K, Siddiqui, J & Haase, G 2017, Package reliability: How can we use ideas/methods from semiconductor reliability in package reliability? in 2017 IEEE International Integrated Reliability Workshop, IIRW 2017. IEEE International Integrated Reliability Workshop Final Report, vol. 2017-October, Institute of Electrical and Electronics Engineers Inc., pp. 1-5, 2017 IEEE International Integrated Reliability Workshop, IIRW 2017, South Lake Tahoe, United States, 10/8/17. https://doi.org/10.1109/IIRW.2017.8361249

Package reliability: How can we use ideas/methods from semiconductor reliability in package reliability? / Kopley, Tom; Pozder, Scott; Anselm, Martin et al.
2017 IEEE International Integrated Reliability Workshop, IIRW 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-5 (IEEE International Integrated Reliability Workshop Final Report; Vol. 2017-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Package reliability

T2 - 2017 IEEE International Integrated Reliability Workshop, IIRW 2017

AU - Kopley, Tom

AU - Pozder, Scott

AU - Anselm, Martin

AU - Justison, Patrick

AU - Ring, Matt

AU - Beckmann, Karsten

AU - Siddiqui, Jeff

AU - Haase, Gaddi

PY - 2017/7/2

Y1 - 2017/7/2

N2 - Are the fields of fracture mechanics, rheology, etc. good enough to address issues In package reliability? No: JEDEC specs all based on DIP wirebond packages. Are we using results from these fields enough or most effectively? Not addressed. Biggest difference with wafer reliability is stressors on chip are local (E-field, temperature), which stressors in a package are mechanical stress, which is resultant of the entire package materials' CTE.

AB - Are the fields of fracture mechanics, rheology, etc. good enough to address issues In package reliability? No: JEDEC specs all based on DIP wirebond packages. Are we using results from these fields enough or most effectively? Not addressed. Biggest difference with wafer reliability is stressors on chip are local (E-field, temperature), which stressors in a package are mechanical stress, which is resultant of the entire package materials' CTE.

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DO - 10.1109/IIRW.2017.8361249

M3 - Conference contribution

T3 - IEEE International Integrated Reliability Workshop Final Report

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BT - 2017 IEEE International Integrated Reliability Workshop, IIRW 2017

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 8 October 2017 through 12 October 2017

ER -

Kopley T, Pozder S, Anselm M, Justison P, Ring M, Beckmann K et al. Package reliability: How can we use ideas/methods from semiconductor reliability in package reliability? In 2017 IEEE International Integrated Reliability Workshop, IIRW 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1-5. (IEEE International Integrated Reliability Workshop Final Report). doi: 10.1109/IIRW.2017.8361249

Package reliability: How can we use ideas/methods from semiconductor reliability in package reliability?

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