TY - GEN
T1 - PASNet
T2 - 60th ACM/IEEE Design Automation Conference, DAC 2023
AU - Peng, Hongwu
AU - Zhou, Shanglin
AU - Luo, Yukui
AU - Xu, Nuo
AU - Duan, Shijin
AU - Ran, Ran
AU - Zhao, Jiahui
AU - Wang, Chenghong
AU - Geng, Tong
AU - Wen, Wujie
AU - Xu, Xiaolin
AU - Ding, Caiwen
N1 - Publisher Copyright: © 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Two-party computation (2PC) is promising to enable privacy-preserving deep learning (DL). However, the 2PC-based privacy-preserving DL implementation comes with high comparison protocol overhead from the non-linear operators. This work presents PASNet, a novel systematic framework that enables low latency, high energy efficiency & accuracy, and security-guaranteed 2PC-DL by integrating the hardware latency of the cryptographic building block into the neural architecture search loss function. We develop a cryptographic hardware scheduler and the corresponding performance model for Field Programmable Gate Arrays (FPGA) as a case study. The experimental results demonstrate that our light-weighted model PASNet-A and heavily-weighted model PASNet-B achieve 63 ms and 228 ms latency on private inference on ImageNet, which are 147 and 40 times faster than the SOTA CryptGPU system, and achieve 70.54% & 78.79% accuracy and more than 1000 times higher energy efficiency. The pretrained PASNet models and test code can be found on Github1.
AB - Two-party computation (2PC) is promising to enable privacy-preserving deep learning (DL). However, the 2PC-based privacy-preserving DL implementation comes with high comparison protocol overhead from the non-linear operators. This work presents PASNet, a novel systematic framework that enables low latency, high energy efficiency & accuracy, and security-guaranteed 2PC-DL by integrating the hardware latency of the cryptographic building block into the neural architecture search loss function. We develop a cryptographic hardware scheduler and the corresponding performance model for Field Programmable Gate Arrays (FPGA) as a case study. The experimental results demonstrate that our light-weighted model PASNet-A and heavily-weighted model PASNet-B achieve 63 ms and 228 ms latency on private inference on ImageNet, which are 147 and 40 times faster than the SOTA CryptGPU system, and achieve 70.54% & 78.79% accuracy and more than 1000 times higher energy efficiency. The pretrained PASNet models and test code can be found on Github1.
KW - FPGA
KW - Multi Party Computation
KW - Neural Architecture Search
KW - Polynomial Activation Function
KW - Privacy-Preserving in Machine Learning
KW - Software/Hardware Co-design
UR - https://www.scopus.com/pages/publications/85171248122
U2 - 10.1109/DAC56929.2023.10247663
DO - 10.1109/DAC56929.2023.10247663
M3 - Conference contribution
T3 - Proceedings - Design Automation Conference
BT - 2023 60th ACM/IEEE Design Automation Conference, DAC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 July 2023 through 13 July 2023
ER -