Pipelined ADC based design of bandpass ΔΣ-ADC

V. Sarma; B. Sahoo

doi:10.1049/el.2013.0739

Pipelined ADC based design of bandpass ΔΣ-ADC

V. Sarma
, B. Sahoo

Department of Electrical Engineering

University at Buffalo

Amrita Vishwa Vidyapeetham

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

A high-speed, large dynamic range f_S/4 bandpass ΔΣ-modulator using a first-order error-feedback loop is proposed. The internal quantiser is realised using a high-speed pipelined ADC. Error feedback is achieved by exploiting the implicit latency in a pipelined ADC. The proposed architecture achieves an SNR of 94 dB with an OSR of 32.

Original language	English
Pages (from-to)	666-667
Number of pages	2
Journal	Electronics Letters
Volume	49
Issue number	10
DOIs	https://doi.org/10.1049/el.2013.0739
State	Published - May 9 2013

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10.1049/el.2013.0739

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abstract = "A high-speed, large dynamic range fS/4 bandpass ΔΣ-modulator using a first-order error-feedback loop is proposed. The internal quantiser is realised using a high-speed pipelined ADC. Error feedback is achieved by exploiting the implicit latency in a pipelined ADC. The proposed architecture achieves an SNR of 94 dB with an OSR of 32.",

author = "V. Sarma and B. Sahoo",

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AB - A high-speed, large dynamic range fS/4 bandpass ΔΣ-modulator using a first-order error-feedback loop is proposed. The internal quantiser is realised using a high-speed pipelined ADC. Error feedback is achieved by exploiting the implicit latency in a pipelined ADC. The proposed architecture achieves an SNR of 94 dB with an OSR of 32.

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Pipelined ADC based design of bandpass ΔΣ-ADC

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