Post-CMOS graphene device integration

Moore's Law is rapidly approaching scalability limits using current complimentary metal-oxide semiconductor (CMOS) techniques. Graphene presents unique properties that may allow the industry to continue down the path of device scaling based on previously unexplored state variables. This work details the initial integration steps pursued for development of a post-CMOS graphene device using a four layer mask set and commercially available 300mm semiconductor equipment. The integration builds a testable graphene p-n junction split gate structure. Results are presented detailing progress in development and physical characterization of the process modules required in fabricating a first-run feasibility graphene device structure. In addition, graphene metrology techniques are discussed. The data summary supports the future ability to build an electrically testable graphene p-n junction split gate structure.