Post-layout simulation time reduction for phase-locked loop frequency synthesizer using system identification techniques

Lechang Liu; Ramesh Pokharel

doi:10.1109/TCAD.2014.2354291

Post-layout simulation time reduction for phase-locked loop frequency synthesizer using system identification techniques

Lechang Liu
, Ramesh Pokharel

Electrical and Computer Eng

Binghamton University

Kyushu University

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

Compact model extraction of phase-locked loop (PLL) frequency synthesizer using system identification techniques is proposed to reduce post-layout simulation time. This is the first published compact model for PLL using system identification techniques. It features an autoregressive exogenous model for the charge pump and the loop filter with a lookup table for nonlinearity compensation and a radial basis function neural network for the voltage-controlled oscillator with nonlinear frequency-voltage relationship, thereby reducing the post-layout simulation time to 26% of the original circuits with the accuracy of 93%.

Original language	English
Article number	6926919
Pages (from-to)	1751-1755
Number of pages	5
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	33
Issue number	11
DOIs	https://doi.org/10.1109/TCAD.2014.2354291
State	Published - Nov 1 2014

Keywords

Autoregressive exogenous model (ARX)
compact model
neural network
phase-locked loop
system identification

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10.1109/TCAD.2014.2354291

Cite this

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title = "Post-layout simulation time reduction for phase-locked loop frequency synthesizer using system identification techniques",

abstract = "Compact model extraction of phase-locked loop (PLL) frequency synthesizer using system identification techniques is proposed to reduce post-layout simulation time. This is the first published compact model for PLL using system identification techniques. It features an autoregressive exogenous model for the charge pump and the loop filter with a lookup table for nonlinearity compensation and a radial basis function neural network for the voltage-controlled oscillator with nonlinear frequency-voltage relationship, thereby reducing the post-layout simulation time to 26\% of the original circuits with the accuracy of 93\%.",

keywords = "Autoregressive exogenous model (ARX), compact model, neural network, phase-locked loop, system identification",

author = "Lechang Liu and Ramesh Pokharel",

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N2 - Compact model extraction of phase-locked loop (PLL) frequency synthesizer using system identification techniques is proposed to reduce post-layout simulation time. This is the first published compact model for PLL using system identification techniques. It features an autoregressive exogenous model for the charge pump and the loop filter with a lookup table for nonlinearity compensation and a radial basis function neural network for the voltage-controlled oscillator with nonlinear frequency-voltage relationship, thereby reducing the post-layout simulation time to 26% of the original circuits with the accuracy of 93%.

AB - Compact model extraction of phase-locked loop (PLL) frequency synthesizer using system identification techniques is proposed to reduce post-layout simulation time. This is the first published compact model for PLL using system identification techniques. It features an autoregressive exogenous model for the charge pump and the loop filter with a lookup table for nonlinearity compensation and a radial basis function neural network for the voltage-controlled oscillator with nonlinear frequency-voltage relationship, thereby reducing the post-layout simulation time to 26% of the original circuits with the accuracy of 93%.

KW - Autoregressive exogenous model (ARX)

KW - compact model

KW - neural network

KW - phase-locked loop

KW - system identification

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JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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M1 - 6926919

ER -

Post-layout simulation time reduction for phase-locked loop frequency synthesizer using system identification techniques

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Keywords

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