Power constrained test scheduling with dynamically varied TAM

Dan Zhao; S. Upadhyaya

doi:10.1109/VTEST.2003.1197663

Power constrained test scheduling with dynamically varied TAM

Dan Zhao
, S. Upadhyaya

Department of Computer Science and Engineering

University at Buffalo

SUNY Buffalo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

27 Scopus citations

Abstract

In this paper we present a novel scheduling algorithm for testing embedded core-based SoCs. Given test conflicts, power consumption limitation and top level test access mechanism (TAM) constraint, we handle the constrained scheduling in a unique way that adaptively assigns the cores in parallel to the TAMs with variable width and concurrently executes the test sets by dynamic test partitioning, thus reducing the test cost in terms of the overall test time. Through simulation, we show that up to 30% of SoC testing time reduction can be achieved by using our scheduling approach.

Original language	English
Title of host publication	Proceedings - 21st IEEE VLSI Test Symposium, VTS 2003
Publisher	IEEE Computer Society
Pages	273-278
Number of pages	6
ISBN (Electronic)	0769519245
DOIs	https://doi.org/10.1109/VTEST.2003.1197663
State	Published - 2003
Event	21st IEEE VLSI Test Symposium, VTS 2003 - Napa Valley, United States Duration: Apr 27 2003 → May 1 2003

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium
Volume	2003-January

Conference

Conference	21st IEEE VLSI Test Symposium, VTS 2003
Country/Territory	United States
City	Napa Valley
Period	04/27/03 → 05/1/03

Keywords

Bandwidth
Computer science
Costs
Dynamic scheduling
Energy consumption
Job shop scheduling
Power engineering and energy
Processor scheduling
Scheduling algorithm
System testing

Access to Document

10.1109/VTEST.2003.1197663

Cite this

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title = "Power constrained test scheduling with dynamically varied TAM",

abstract = "In this paper we present a novel scheduling algorithm for testing embedded core-based SoCs. Given test conflicts, power consumption limitation and top level test access mechanism (TAM) constraint, we handle the constrained scheduling in a unique way that adaptively assigns the cores in parallel to the TAMs with variable width and concurrently executes the test sets by dynamic test partitioning, thus reducing the test cost in terms of the overall test time. Through simulation, we show that up to 30\% of SoC testing time reduction can be achieved by using our scheduling approach.",

keywords = "Bandwidth, Computer science, Costs, Dynamic scheduling, Energy consumption, Job shop scheduling, Power engineering and energy, Processor scheduling, Scheduling algorithm, System testing",

author = "Dan Zhao and S. Upadhyaya",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 21st IEEE VLSI Test Symposium, VTS 2003 ; Conference date: 27-04-2003 Through 01-05-2003",

year = "2003",

doi = "10.1109/VTEST.2003.1197663",

language = "English",

series = "Proceedings of the IEEE VLSI Test Symposium",

publisher = "IEEE Computer Society",

pages = "273--278",

booktitle = "Proceedings - 21st IEEE VLSI Test Symposium, VTS 2003",

address = "United States",

}

Zhao, D & Upadhyaya, S 2003, Power constrained test scheduling with dynamically varied TAM. in Proceedings - 21st IEEE VLSI Test Symposium, VTS 2003., 1197663, Proceedings of the IEEE VLSI Test Symposium, vol. 2003-January, IEEE Computer Society, pp. 273-278, 21st IEEE VLSI Test Symposium, VTS 2003, Napa Valley, United States, 04/27/03. https://doi.org/10.1109/VTEST.2003.1197663

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AU - Upadhyaya, S.

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N2 - In this paper we present a novel scheduling algorithm for testing embedded core-based SoCs. Given test conflicts, power consumption limitation and top level test access mechanism (TAM) constraint, we handle the constrained scheduling in a unique way that adaptively assigns the cores in parallel to the TAMs with variable width and concurrently executes the test sets by dynamic test partitioning, thus reducing the test cost in terms of the overall test time. Through simulation, we show that up to 30% of SoC testing time reduction can be achieved by using our scheduling approach.

AB - In this paper we present a novel scheduling algorithm for testing embedded core-based SoCs. Given test conflicts, power consumption limitation and top level test access mechanism (TAM) constraint, we handle the constrained scheduling in a unique way that adaptively assigns the cores in parallel to the TAMs with variable width and concurrently executes the test sets by dynamic test partitioning, thus reducing the test cost in terms of the overall test time. Through simulation, we show that up to 30% of SoC testing time reduction can be achieved by using our scheduling approach.

KW - Bandwidth

KW - Computer science

KW - Costs

KW - Dynamic scheduling

KW - Energy consumption

KW - Job shop scheduling

KW - Power engineering and energy

KW - Processor scheduling

KW - Scheduling algorithm

KW - System testing

UR - https://www.scopus.com/pages/publications/84943556981

U2 - 10.1109/VTEST.2003.1197663

DO - 10.1109/VTEST.2003.1197663

M3 - Conference contribution

T3 - Proceedings of the IEEE VLSI Test Symposium

SP - 273

EP - 278

BT - Proceedings - 21st IEEE VLSI Test Symposium, VTS 2003

PB - IEEE Computer Society

T2 - 21st IEEE VLSI Test Symposium, VTS 2003

Y2 - 27 April 2003 through 1 May 2003

ER -

Power constrained test scheduling with dynamically varied TAM

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Keywords

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