Predictive model for optimized design parameters in flip-chip packages

An analytical model is developed to predict the out of plane deformation in multilayered thin stacks subjected to uniform temperature loading. CTE mismatches among the components (chip, substrate, underfill, flip-chip interconnect or C4s) are the driving force for both first and second levels interconnect reliability concerns. The first level failure includes die cracking and underfill delamination whereas the second level interconnects are concerned with the BGA fatigue and non-wetting or partial wetting during the assembly process. In this study, a proper formula for effective moduli of the complex geometry, such as solder (C4)/underfill layer, is presented. An analytical formulation for the out of plane displacement of the chip substrate structure under temperature variation ΔT of as high as 205°C as expected in lead (Pb) free solder applications during reflow, is developed using the effective moduli. The warpage resulting from the analytical formulation is compared with the two-dimensional and three-dimensional finite element analysis (FEA). The importance and challenges in the analytical modeling aspect of the thermo-mechanical behavior of the flip chip or chip on board assembly is emphasized. The study helps to design more reliable components or assemblies with the design parameters being optimized in the early stage of the development.