TY - GEN
T1 - Programmable memory BIST and a new synthesis framework
AU - Zarrineh, Kamran
AU - Upadhyaya, Shambhu J.
PY - 1999
Y1 - 1999
N2 - The development of two programmable memory BIST architecture is first reported. A memory synthesis framework which can automatically generate, verify and insert programmable as well as non-programmable BIST units is developed as a vehicle to efficiently integrate BIST architectures in today's memory-intensive systems. Custom memory test algorithms could be loaded in the developed programmable BIST unit and therefore any type of memory test algorithm could be realized. The flexibility and efficiency of the framework are demonstrated by showing that these memory BIST units could be generated, functionally verified and inserted in a short time.
AB - The development of two programmable memory BIST architecture is first reported. A memory synthesis framework which can automatically generate, verify and insert programmable as well as non-programmable BIST units is developed as a vehicle to efficiently integrate BIST architectures in today's memory-intensive systems. Custom memory test algorithms could be loaded in the developed programmable BIST unit and therefore any type of memory test algorithm could be realized. The flexibility and efficiency of the framework are demonstrated by showing that these memory BIST units could be generated, functionally verified and inserted in a short time.
UR - https://www.scopus.com/pages/publications/0032597601
M3 - Conference contribution
SN - 0780357639
T3 - Proceedings - Annual International Conference on Fault-Tolerant Computing
SP - 352
EP - 355
BT - Proceedings - Annual International Conference on Fault-Tolerant Computing
PB - IEEE
T2 - Proceedings of the 1999 29th Annual International Symposium on Fault-Tolerant Computing (FTCS-29)
Y2 - 15 June 1999 through 18 June 1999
ER -