TY - GEN
T1 - Reconfigurable graphene logic device based on tilted P-N junctions
AU - Tanachutiwat, Sansiri
AU - Lee, Ji Ung
AU - Wang, Wei
PY - 2011
Y1 - 2011
N2 - In this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using co-planar split gates that modulate the properties that are unique to graphene, including ambipolar conduction, electrostatic doping, and angular dependent carrier reflection. In addition, the use of these control gates can dynamically change the operation of the device, leading to reconfigurable multifunctional logic. A device model is derived from carrier transmission probability across the p-n junction for allowing quantitative comparison to CMOS logic. Based on this model, we show that the proposed graphene logic has significant advantages over CMOS gate in terms of area, delay, power, and signal restoration. Furthermore, the device utilizes a large graphene sheet with minimal patterning, allowing feasible integration with CMOS circuits, for potential CMOS-graphene hybrid circuits.
AB - In this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using co-planar split gates that modulate the properties that are unique to graphene, including ambipolar conduction, electrostatic doping, and angular dependent carrier reflection. In addition, the use of these control gates can dynamically change the operation of the device, leading to reconfigurable multifunctional logic. A device model is derived from carrier transmission probability across the p-n junction for allowing quantitative comparison to CMOS logic. Based on this model, we show that the proposed graphene logic has significant advantages over CMOS gate in terms of area, delay, power, and signal restoration. Furthermore, the device utilizes a large graphene sheet with minimal patterning, allowing feasible integration with CMOS circuits, for potential CMOS-graphene hybrid circuits.
UR - https://www.scopus.com/pages/publications/84859052125
U2 - 10.1557/opl.2011.751
DO - 10.1557/opl.2011.751
M3 - Conference contribution
SN - 9781618394996
T3 - Materials Research Society Symposium Proceedings
SP - 61
EP - 72
BT - Carbon-Based Electronic Devices - Processing, Performance and Reliability
T2 - 2010 MRS Fall Meeting
Y2 - 29 November 2010 through 3 December 2010
ER -