@inproceedings{648149c7e1dc4d17a4a2222a1c2b966b,
title = "Resource allocation methodology for through silicon vias and sleep transistors in 3D ICs",
abstract = "A methodology and analytic expressions are proposed to appropriately allocate the available physical area to through silicon vias (TSVs) and sleep transistors in three-dimensional (3D) ICs with power gating. Power supply noise is minimized by the proposed resource allocation methodology while satisfying the required constraints on leakage current and turn-on time. A comprehensive simulation setup of a three plane 3D IC is developed to evaluate the accuracy and efficacy of the proposed methodology. The proposed expressions exhibit an error of 4\% as compared to simulation results. The simulation results also demonstrate that the power supply noise is reduced by more than 46\% while satisfying both turn-on time and leakage current.",
keywords = "3D IC, Power gating, TSV, sleep transistor",
author = "Hailang Wang and Emre Salman",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 16th International Symposium on Quality Electronic Design, ISQED 2015 ; Conference date: 02-03-2015 Through 04-03-2015",
year = "2015",
month = apr,
day = "13",
doi = "10.1109/ISQED.2015.7085481",
language = "English",
series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",
publisher = "IEEE Computer Society",
pages = "528--532",
booktitle = "Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015",
}