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Response-pipelined CAM chips-Building blocks for large associated arrays

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Abstract

The authors introduce the architecture of a new type of fully parallel content addressable memory chips that serve as building blocks for large associated arrays. These new chips can be easily cascaded to increase the logical word size or the number of words and yet allow the search rate to be maintained constant irrespective of the logical word size or word count. Prototype CMOS implementations of the architecture have been tested and evaluated and demonstrated significant speedups compared to other existing associative hardware.

Original languageEnglish
Title of host publicationProceedings of International Conference on Application Specific Array Processors, ASAP 1993
EditorsLuigi Dadda, Benjamin Wah
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages144-147
Number of pages4
ISBN (Electronic)0818634928
DOIs
StatePublished - 1993
Event1993 International Conference on Application Specific Array Processors, ASAP 1993 - Venice, Italy
Duration: Oct 25 1993Oct 27 1993

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Conference

Conference1993 International Conference on Application Specific Array Processors, ASAP 1993
Country/TerritoryItaly
CityVenice
Period10/25/9310/27/93

Keywords

  • Array Processing
  • Associative Arrays
  • Associative Memory
  • Content-Addressable Memory

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