Scalable, pipelined, CMOS VLSI content addressable memory chips - Architecture and implementation

Kanad Ghose; Arun Gupta

doi:10.1109/ICVD.1992.658040

Scalable, pipelined, CMOS VLSI content addressable memory chips - Architecture and implementation

Kanad Ghose
, Arun Gupta

School of Computing

Binghamton University

National Instruments

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Content Addressable Memories (CAMs) are useful in search-intensive applications such as mle-based systems, database applications and pattern matching. In this paper, we introduce the design and CMOS VLSI implementation of two CAM chips that allow cascading to increase tho word-size and the number of words, and yet maintain the soarch rate constant through the use of rcsponso pipelining. These features make our proposed chips very unique and mako them usable in a targe variety of applications involving searches on w>de words. Wo also present several practical design tradooffs that led to the final versions of the chips.

Original language	English
Title of host publication	Proceedings - VLSI Design 1992
Subtitle of host publication	The 5th International Conference on VLSI Design, ICVD 1992
Publisher	IEEE Computer Society
Pages	161-166
Number of pages	6
ISBN (Electronic)	0818624655
DOIs	https://doi.org/10.1109/ICVD.1992.658040
State	Published - 1992
Event	5th International Conference on VLSI Design, ICVD 1992 - Banglore, India Duration: Jan 4 1992 → Jan 7 1992

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design

Conference

Conference	5th International Conference on VLSI Design, ICVD 1992
Country/Territory	India
City	Banglore
Period	01/4/92 → 01/7/92

Access to Document

10.1109/ICVD.1992.658040

Cite this

Ghose, K., & Gupta, A. (1992). Scalable, pipelined, CMOS VLSI content addressable memory chips - Architecture and implementation. In Proceedings - VLSI Design 1992: The 5th International Conference on VLSI Design, ICVD 1992 (pp. 161-166). Article 658040 (Proceedings of the IEEE International Conference on VLSI Design). IEEE Computer Society. https://doi.org/10.1109/ICVD.1992.658040

@inproceedings{13b1c59f778e4bc2914de4f8fe969000,

title = "Scalable, pipelined, CMOS VLSI content addressable memory chips - Architecture and implementation",

abstract = "Content Addressable Memories (CAMs) are useful in search-intensive applications such as mle-based systems, database applications and pattern matching. In this paper, we introduce the design and CMOS VLSI implementation of two CAM chips that allow cascading to increase tho word-size and the number of words, and yet maintain the soarch rate constant through the use of rcsponso pipelining. These features make our proposed chips very unique and mako them usable in a targe variety of applications involving searches on w>de words. Wo also present several practical design tradooffs that led to the final versions of the chips.",

author = "Kanad Ghose and Arun Gupta",

note = "Publisher Copyright: {\textcopyright} 1991 IEEE.; 5th International Conference on VLSI Design, ICVD 1992 ; Conference date: 04-01-1992 Through 07-01-1992",

year = "1992",

doi = "10.1109/ICVD.1992.658040",

language = "English",

series = "Proceedings of the IEEE International Conference on VLSI Design",

publisher = "IEEE Computer Society",

pages = "161--166",

booktitle = "Proceedings - VLSI Design 1992",

}

Ghose, K & Gupta, A 1992, Scalable, pipelined, CMOS VLSI content addressable memory chips - Architecture and implementation. in Proceedings - VLSI Design 1992: The 5th International Conference on VLSI Design, ICVD 1992., 658040, Proceedings of the IEEE International Conference on VLSI Design, IEEE Computer Society, pp. 161-166, 5th International Conference on VLSI Design, ICVD 1992, Banglore, India, 01/4/92. https://doi.org/10.1109/ICVD.1992.658040

Scalable, pipelined, CMOS VLSI content addressable memory chips - Architecture and implementation. / Ghose, Kanad; Gupta, Arun.
Proceedings - VLSI Design 1992: The 5th International Conference on VLSI Design, ICVD 1992. IEEE Computer Society, 1992. p. 161-166 658040 (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Scalable, pipelined, CMOS VLSI content addressable memory chips - Architecture and implementation

AU - Ghose, Kanad

AU - Gupta, Arun

PY - 1992

Y1 - 1992

N2 - Content Addressable Memories (CAMs) are useful in search-intensive applications such as mle-based systems, database applications and pattern matching. In this paper, we introduce the design and CMOS VLSI implementation of two CAM chips that allow cascading to increase tho word-size and the number of words, and yet maintain the soarch rate constant through the use of rcsponso pipelining. These features make our proposed chips very unique and mako them usable in a targe variety of applications involving searches on w>de words. Wo also present several practical design tradooffs that led to the final versions of the chips.

AB - Content Addressable Memories (CAMs) are useful in search-intensive applications such as mle-based systems, database applications and pattern matching. In this paper, we introduce the design and CMOS VLSI implementation of two CAM chips that allow cascading to increase tho word-size and the number of words, and yet maintain the soarch rate constant through the use of rcsponso pipelining. These features make our proposed chips very unique and mako them usable in a targe variety of applications involving searches on w>de words. Wo also present several practical design tradooffs that led to the final versions of the chips.

UR - https://www.scopus.com/pages/publications/84908833837

U2 - 10.1109/ICVD.1992.658040

DO - 10.1109/ICVD.1992.658040

M3 - Conference contribution

T3 - Proceedings of the IEEE International Conference on VLSI Design

SP - 161

EP - 166

BT - Proceedings - VLSI Design 1992

PB - IEEE Computer Society

T2 - 5th International Conference on VLSI Design, ICVD 1992

Y2 - 4 January 1992 through 7 January 1992

ER -

Scalable, pipelined, CMOS VLSI content addressable memory chips - Architecture and implementation

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this