Smart Three Axis Compliant (STAC) interconnect: An ultra-high density MEMS based interconnect for wafer-level ultra-thin die stacking technology

This paper describes a novel Smart Three Axis Compliant (STAC) interconnect targeted to revolutionize chip-to-chip and chip-to-board high-density 3D integration for ultra-thin Si dies (≤75μm) at the wafer level. The STAC interconnect is a three dimensionally compliant interconnect which allows stacked ultra-thin chips to move or flex freely during operation with negligible stress imposed on the die. The paper will show that these interconnects can accommodate mismatches of board or package coefficient of thermal expansion (GTE) from chip CTE. STAG interconnects are fabricated using MEMS technologies to support super-fine-pitch (≈20μm pitch) interconnection. These interconnects are batch processed and die containing them can be stacked either at the wafer-level or at the die-level.