Stochastic behavior of a CMOS inverter

As feature sizes of integrated circuits continue to shrink and demand for low power operation continues to increase, power supply voltages may eventually be reduced to the level where noise becomes significant compared with signals. This would cause digital logic circuits to exhibit non-deterministic behavior. In this paper, we study the stochastic behavior of simple digital circuits operating at low power supply voltages. We develop a method for modelling the stochastic behavior of circuits and apply the method to a CMOS inverter. We use numerical simulations of stochastic differential equations to obtain time-domain transient analysis of the CMOS inverter and magnitude statistics from multiple sample paths. Further, we derive the output distribution at steady state from first principles. We characterize the switching error and the information transmission based on the output steady state distribution. This study provides a detailed understanding of how noise affects the operation of the CMOS inverter at low power supply voltages. The method we develop here can also be extended to other circuits where stochastic sample paths and sample statistics are necessary to characterize the circuits. Traditional frequency domain noise analysis is not adequate to provide this information.