Switched current integrating sampler for time interleaved ADCs

With the continued improvements in time-interleaved ADC (TIADC) performance, the power of voltage buffer in input track-and-hold amplifier (THA) driving the ADC input capacitor becomes a major component of the overall power consumption. To reduce the input buffer power consumption, switched current integrating sampler (CIS) is proposed. Switched CIS is analyzed and compared to the conventional THAs. To fairly compare the power consumption of both circuits under different operating conditions, power consumption equations are derived. Circuit level simulations are performed to validate these equations. The switched CIS is shown to consume approximately 50% of the conventional switched THA power for medium resolution i.e., < 8b TIADCs.