Abstract
This paper presents two heuristics for automatic hardware/software partitioning of system level specifications Partitioning is performed at the granularity of blocks, loops, subprograms, and processes with the objective of performance optimization with a limited hardware and software cost. We define the metric values for partitioning and develop a cost function that guides partitioning towards the desired objective. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria during partitioning. Two heuristics for hardware/software partitioning, formulated as a graph partitioning problem, are presented: one based on simulated annealing and the other on tabu search. Results of extensive experiments, including real-life examples, show the clear superiority of the tabu search based algorithm.
| Original language | English |
|---|---|
| Pages (from-to) | 5-32 |
| Number of pages | 28 |
| Journal | Design Automation for Embedded Systems |
| Volume | 2 |
| Issue number | 1 |
| DOIs | |
| State | Published - 1997 |
Keywords
- Co-synthesis
- Hardware/software partitioning
- Iterative improvement heuristics
- Simulated annealing
- Tabu search
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