Abstract
Technology scaling continues to improve transistor performance and integration to realize complex systems and added functionality in SoC designs. This reduces the energy consumed with a 30% speed improvement per technology generation. The scaling, however, comes with some adverse effects posing perceived barriers. In this paper, we discuss the design challenges in Ultra Deep Submicron (UDSM) technologies and the scaling problems in SoC circuits for clocking and synchronization. This includes delay variations and functional errors due to various types of noise sources. Correct clocking and synchronization can be achieved through innovative strategies that work at all levels of abstraction.
| Original language | English |
|---|---|
| Pages (from-to) | 520-527 |
| Number of pages | 8 |
| Journal | Proceedings of the IEEE International Conference on VLSI Design |
| Volume | 17 |
| State | Published - 2004 |
| Event | Proceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design - Mumbai, India Duration: Jan 5 2004 → Jan 9 2004 |
Fingerprint
Dive into the research topics of 'System-on-chip (SOC): Clocking and synchronization issues'. Together they form a unique fingerprint.Cite this
- APA
- Author
- BIBTEX
- Harvard
- Standard
- RIS
- Vancouver