@inproceedings{dcf532eb90ab443bb189424d184e9781,
title = "Usage of application-specific switching activity for energy minimization of arithmetic units",
abstract = "This paper presents a delay constraint power minimization technique for logic incorporating dual supply voltages. The power is reduced by selecting supply voltage according to switching activity of the subunits. The technique employs energy and delay models of arithmetic units with array structure. The supply voltage is selected to reduce power consumption while maintaining propagation delay constraint. The model characterization is done with Verilog simulation where subunits are designed with Cadence and HSPICE using 0.35 μm CMOS process. We applied the technique on multiplier of general purpose DSP processors and CORDIC. The results obtained from the proposed method is discussed.",
author = "Chin, \{Shu Shin\} and Sangjin Hong and Suhwan Kim",
year = "2004",
language = "English",
isbn = "0769520979",
series = "Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design",
pages = "158--163",
editor = "A. Smailagic and M. Bayoumi",
booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI",
note = "Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design ; Conference date: 19-02-2004 Through 20-02-2004",
}