VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks

A VLSI implementation of a flexible router scheme for parallel interconnection network architectures is presented in this paper. The router implements implicit oblivious routing algorithms in 1.5 clock cycles, this being the fastest approach for flexible routers. To further increase performance, the router operation has been made pipelined with a throughput of 1 routing decision per cycle. The implementation is based on a combination of a content addressable memory that supports per entry unique bit masking, a fast priority scheme that allows only one entry to be selected, and a memory that stores the port assignment. The number of required CAM entries is extremely small; it is of the same order as the output ports (or node degree).