Yield Enhancement of Field Programmable Logic Arrays by Inherent Component Redundancy

Techniques for the yield enhancement of VLSI chips often employ imposed component redundancy where the redundant hardware is implemented on the chip. A complete technique for the yield enhancement of field programmable logic arrays (FPLA’s) that does not use any additional components is presented in this paper. In our approach, the inherent sparsity (absence of devices at crosspoints) of programmable logic arrays (PLA's) is utilized to mask out certain types of manufacturing defects within the unprogrammed FPLA's. This leads to the reclaim of chips which are otherwise discarded. Two categories of faults called type 1 and type 2, are considered in this paper. Type 1 faults, which can be diagnosed a priori are considered first. After diagnosing type 1 faults, the mask can be reconfigured around the faulty crosspoints. A new streamlined bipartite matching algorithm is presented to enhance the speed of this reconfiguration. The uniqueness of our approach is that the programming of an FPLA is formulated as a graph theoretic problem for which a polynomial time solution exists. Type 2 faults in general cannot be diagnosed a priori. Therefore, a dynamic technique is presented for the repair of type 2 faults. In this technique, unused product lines of the FPLA are utilized for the repair. With a sufficient number of excess product lines, we show that a defective FPLA is guaranteed to be rendered usable. We obtain a probability measure for the usability of defective FPLA's both with and without the implementation of this technique. Computer studies have shown that FPLA's with even a large number of defects can be successfully repaired, thereby increasing the yield.